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As shown in the accompanying tables, the
performance improvements in GaAs based devices can be substantial, with
the potential for another 5-10X improvement in GaN devices.
 Technology
The material properties of
III–V compounds, such as GaAs and InP, allow the component/device
designer to miniaturize devices, resulting in multiple devices on a
single chip and increased functionality over a smaller working area. To
date, this has been successfully applied only to low voltage
applications, particularly in the wireless communications area. The
benefits of these compounds are also useful at higher voltages and
powers. However, as voltage, power, and/or switching frequency increase,
device performance and efficiency are negatively impacted by voltage
breakdown. The Welch Allyn technology essentially eliminates this issue.
As shown in the schematic
above, a "dipole barrier layer" is inserted between the substrate (the
semi-insulating and structural support base of a FET) and the channel
layers (where the current flows) to prevent the flow of current through
the substrate and to prevent the movement of current carriers out of the
substrate into the channel layer. This results in higher voltages of
operation. There are three to four known methods of producing the dipole
barrier, which in all cases, sets up an electronic barrier that is
charge neutral and confines current flow to the channel layer.
The technology is covered
by U.S. Patent
6,150,680, along with four associated foreign applications.
Using a unique design approach, along with variations in processing,
improvements at higher voltage and power can be achieved using III–V
compounds such as GaAs, InP, and potentially GaN and SiC.
Contact:
Dr. Stephen P. Weeks, President
First Principals, Inc.
1768 East 25th Street
Cleveland, Ohio 44114
216-881-8521 - Phone
216-881-8522 - Fax
Email: spweeks@firstprincipals.com
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